The present invention relates to a semiconductor device having a P channel MOSFET (PMOS) and an N channel MOSFET (NMOS), and more specifically to a semiconductor device of such a type designed to improve a current driving capability.
PMOS and NMOS devices are used in pairs in a H bridge type motor control circuit, as shown in FIG. 5, for driving a load in the form of a DC motor in forward and reverse directions. This circuit includes a first PMOS 60 connected between a power supply terminal 31 and a first terminal of a DC motor 32, a second PMOS 80 connected between the supply terminal 31 and a second terminal of the DC motor 32, a first NMOS 70 connected between the second terminal of the DC motor 32 and a ground terminal, and a second NMOS 90 connected between the first terminal of the DC motor 32 and the ground terminal (earth terminal). The DC motor 32 is driven in the forward direction by a current flowing in a direction A shown in FIG. 5 when the first PMOS 60 and NMOS 70 are turned on. On the other hand, the second PMOS 80 and NMOS 90 turn on and allow a current to flow in a direction B to drive the DC motor 32 in the reverse direction. In either case, the current flows through one pair of the PMOS and NMOS 60 and 70, or 80 and 90.
In this way, a current in the H bridge circuit necessarily flows through a pair of switching devices between the power supply and ground. Such a circuit is called a push-pull circuit. Other examples of the push-pull circuit are a circuit for driving a three-phase motor, and an inverter circuit.
Monolithic integrated circuits having a plurality of MOSFETs formed on and/or within a single semiconductor substrate are very advantageous, as is well known, in reliability and fabricating cost. In general, the monolithic IC technologies use semiconductor substrates, such as silicon substrates, having one major surface which is the (100) crystal plane. The (100) oriented substrates are preferred because the surface mobility of electrons is higher in the (100) plane than in other crystal planes, further because the interface level density (or the interface trap density) is lower in the interface between the (100) silicon plane and a SiO2 film, and further because various data have been accumulated for the widely used (100) wafers.
It is possible to form the PMOS 60 and NMOS 90 shown in FIG. 5 in and on a single crystal semiconductor substrate. In a conventional monolithic IC structure, however, the PMOS and NMOS are arranged so that the currents of the PMOS and NMOS flow in the same direction.
The dependencies of the surface mobilities of electrons and holes on the semiconductor crystal plane orientation are shown in Kischino and Koyanagi "Physics of VLSI Devices (Denshi Zairyo Series)", page 145, published by MARUZEN Co. Ltd. in 1986. According to this document, the (100), (111) and (011) planes have values of the surface mobilities of electrons and holes and the channel resistances of NMOS and PMOS as listed in a table of FIG. 6.
In the table of FIG. 6, it is assumed that the channel resistances of NMOS and PMOS are inversely proportional to the surface mobilities of electrons and holes, respectively, and the channel resistance values are shown by using the channel resistance value of NMOS on the (100) plane as a standard of comparison. On the (011) plane, the surface mobilities differ according to the current direction. FIG. 6 shows the surface mobilities in the direction parallel to the &lt;011&gt; direction on the (011) plane and in the direction perpendicular to the &lt;011&gt; direction on the (011) plane.
As evident from FIG. 6, the (100) plane makes the electron surface mobility higher, and the NMOS channel resistance lower. However, the hole surface mobility is low, and accordingly the PMOS channel resistance is high in the (100) plane. When PMOS and NMOS are integrated into a monolithic circuit of a semiconductor substrate having a surface of the (100) crystal plane, and used in the H-bridge motor control circuit shown in FIG. 5, the total on resistance in the on state for driving the motor is determined by the sum of the channel resistances of PMOS and NMOS, and amounts to as high as 5.6 R. As the total on resistance increases, the current driving capability to the load becomes lower, and the switching devices produce more heat.
According to the table of FIG. 6, the total channel resistances of PMOS and NMOS is lower in the (111) plane than in the (100) plane. Therefore, the use of the (111) plane can reduce the total on resistance. The (111) wafers were used in early P channel enhancement type MOSFET integrated circuits.
The total channel resistance of PMOS and NMOS on the (011) plane is lower, without regard to the current direction, than that of the (111) plane. A conventional monolithic circuit including PMOS and NMOS formed in a (011) semiconductor substrate is disclosed in "Fully Symmetric Cooled CMOS" on (110) plane, M. Aoki, K. Yano, T. Masuhara and K. Shimohigashi, IEEE Transactions on Electron Devices, vol. IE.sup.3 -ED, No. 8, August 1989, pp. 1429-1433. In this semiconductor device, a CMOS inverter is composed of PMOS and NMOS formed in parallel on the (011) surface of the semiconductor substrate. The parallel arrangement of the PMOS and NMOS makes the surface mobilities of both MOS transistors equal. However, this document is silent about the difference of the surface mobilities due to the current direction difference. The PMOS and NMOS are arranged in parallel presumably because the surface mobilities are equal between the PMOS and NMOS when the currents of the PMOS and NMOS both flow in the direction parallel to the &lt;011&gt; direction.
In the direction parallel to the &lt;011&gt; direction on the (011) plane, the hole surface mobility is higher and the electron surface mobility is lower as compared with the direction perpendicular to the &lt;011&gt; direction. As a result, the parallel arrangement of the PMOS and NMOS makes the total on resistance higher and degrades the current driving capability. In the case of the CMOS circuit, the area required to form each MOSFET is inversely proportional to the surface mobility of electrons or holes, and proportional to the channel resistance of PMOS or NMOS. As a result, the parallel arrangement cannot reduce the required area.